Fabrication of semiconductor devices, e.g., transistors, is well known in the art. A background of the fabrication of a semiconductor device, e.g., transistor, is deemed appropriate. FIG. 1 illustrates a cross-section of a semiconductor topography where an oxide layer 4 is formed across a single crystalline substrate 2, e.g., silicon and gallium arsenide. Typically, oxide 4 is comprised of silicon dioxide. A polysilicon layer 6 is then deposited by a variety of techniques, e.g., low pressure chemical vapor deposition (LPCVD), across oxide 4.
FIG. 2 illustrates the formation of a gate conductor 10, a gate oxide 8, and exposed regions 14 and 16 of substrate 2. Portions of polysilicon layer 6 and oxide layer 4 of FIG. 1 may be etched to the underlying silicon substrate 2 thereby resulting in a configuration of FIG. 2. Exposed regions 14 and 16, i.e.,junction regions, are adjacent to gate conductor 10 spaced apart by gate oxide 8. Gate conductor 10 has vertically opposed sidewall surfaces 12 as a result of the etching. Furthermore, gate conductor 10 is separated from substrate 2 by a thin layer of gate oxide 8.
FIG. 3 illustrates the implantation of impurities in regions commonly referred to as lightly doped drain (LDD) regions 18 prior to the formation of a spacer (See FIG. 5) within the upper portion of substrate 2.
FIG. 4 illustrates an etch material 20 that may be grown or deposited across exposed regions 14 and 16 and gate conductor 10. Typically, etch material 20 etches at a slower rate than an overlying, subsequent formed spacer material (See FIG. 5). The thickness of etch material 20 is predetermined so that etch material 20 is not penetrated during the removal of the overlying spacer material.
FIG. 5 illustrates the deposition and partial removal of a spacer material 22 across etch material 20. Typically spacer material 22 is comprised of chemical vapor deposited nitride. After the deposition of spacer material 22, spacer material 22 may be removed using an antisotropic etch process at a faster rate along the horizontal surfaces than the vertical surfaces. Hence, spacer material 22 is primarily retained adjacent to sidewall surfaces 12 of gate conductor 10. The retained portions form what is commonly referred to as spacers 24 and 26. The etch duration is selected to last until the width of the spacers sufficiently masks portions of exposed regions 14 and 16 near the channel.
FIG. 6 illustrates a heavily doped source/drain implant that is forwarded to exposed areas of exposed regions 14 and 16 and to gate conductor 10. The dopants may be n-type, e.g., arsenic and phosphorus, or p-type, e.g., boron and boron difluoride, depending on the desired type of transistor. For example, if n-type dopants are implanted, then the transistor is an n-channel transistor device. If p-type dopants are implanted, then the transistor is a p-channel transistor device. The source/drain implant may be self-aligned to the exposed lateral surfaces of spacers 24 and 26. Thus, a drain region 28 and a source region 30 may be formed within the upper portion of substrate 2 on opposite sides of gate conductor 10. Drain region 28 and source region 30 are spaced from one of the sidewall surfaces 12 of gate conductor 10 by the width of one spacer, 24 and 26, respectively, and the width of the etch material 20 adjacent to the sidewall surfaces 12 of gate conductor 10.
Spacers 24 and 26 effectively control the width of LDD regions 18 by controlling how far drain and source regions 28 and 30 are spaced from the sidewall surfaces 12 of gate conductor 10. The width of LDD regions 18 effectively determines the length of gate conductor 10 which essentially determines the speed of the transistor. Therefore, it is imperative to develop a technique to quantify the width of spacers 24 and 26 and thereby adjust the manufacturing process to control the width of LDD regions 18.
One such technique involves the use of optical instrumentation to measure the thickness of the deposition of the spacer material across the etch material. Unfortunately, the technique indirectly measures the spacer width which results in inaccuracies. Furthermore, optical measurement devices are not accurate to characterize an electrical device because of what is commonly referred to as drift. Drift refers to the random internal changes in the measurement apparatus that affect the accuracy of the measurement.
It would therefore be desirable to quantify the spacer width more accurately and thereby adjust the manufacturing process to effectively control the width of the LDD regions and hence control the speed of the transistor.